Not Applicable
Not Applicable
1. Filed of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for lithographic processing, in which a circuit pattern is transferred onto a semiconductor device.
2. Description of the Related Art
When, in the fabrication of semiconductor devices, a circuit pattern is lithographically transferred to a substrate wafer of a semiconductor device (hereinafter referred to as xe2x80x9cwaferxe2x80x9d), numerous exposure steps and etching steps are necessary. FIG. 2 illustrates a method for transferring a circuit pattern onto an insulating film formed on the wafer. First, in an exposure step, a circuit pattern is transferred onto a photoresist film on the wafer. Then, in an etching step, using the photoresist pattern formed in the exposure step as a mask, a circuit pattern is formed in the insulating film on the wafer. More specifically, in a first exposure process a photoresist film is formed on the wafer by an application process. In a second exposure process, the circuit pattern is transferred to the photoresist using an exposure device. After that, the exposed photoresist is put through a developing process to form a photoresist pattern.
FIG. 3 shows the configuration of a reduction projection exposure device used mainly for the lithographic (hereinafter xe2x80x9cexposurexe2x80x9d) step. With this exposure device, a circuit pattern formed by etching metal on a glass xe2x80x9creticlexe2x80x9d (a mask usually made of quartz glass) is exposed through a reduction lens, to pattern one or more chips on a wafer at a time. By changing the reticles in subsequent exposure steps, the circuit patterns necessary for fabricating a semiconductor device can be formed on the wafer. With the resolution of the circuit pattern and the pattern arrangement that takes place in the exposure steps, it is possible to optimize the illumination conditions of the optical projection system of the exposure device, such as the numerical aperture NA and the illumination coherency "sgr", as well as the photoresist parameters (type, thickness, etc.).
In order to satisfy the electrical properties of a semiconductor device, not only the resolution, but also the variations in the dimensions of the transfer pattern have to be within tolerance ranges. For example, variations in the gate dimension of a transistor may cause variations in the threshold voltage of a transistor, so that variations in the photoresist pattern dimensions have to be set within a certain tolerance range. There are many causes of dimensional fluctuations in the photoresist pattern, such as focus shifts, discrepancies when producing the circuit pattern on the reticles, aberrations in the reduction lens of the exposure device, or variations caused by the application or developing processes. In actuality, the fluctuations in the exposure device are the most important, so that the exposure energy and the offset of the focus when transferring a circuit pattern are set for each reticle, exposure step, and exposure device, and the dimension of the photoresist pattern portion with the smallest margin in the exposure steps (critical dimension, hereinafter referred to as xe2x80x9cCDxe2x80x9d) is adjusted to be within a certain tolerance value. At present, the optimum values for the exposure energy and the focus offset are calculated for each reticle, exposure step and exposure device by measuring the CD of a test wafer that is exposed with different exposure energies and focuses (also called xe2x80x9cextracting the exposure conditionsxe2x80x9d). At this time, a process window of exposure energy and focus, in which the CD values are within a certain tolerance value, is produced, and the central value of that window is taken as the optimum value of exposure energy and focus offset. Moreover, the larger the window, the higher is the margin with respect to CD fluctuations in the exposure step, so that the process window can be used as an assessment index of the exposure step. FIG. 4 illustrates a method for calculating the optimum values of exposure energy and focus offset using the process window for the exposure step. The process window of the exposure energy and focus is calculated using the CD values of a test wafer that is exposure processed while changing the exposure energy and the focus offset within a certain tolerance. Here, an example is shown in which, for the same reticle, the process windows as well as the final optimum exposure energy and focus offset differ depending on whether device A or device B is used for the exposure step.
On the other hand, fabrication for multiple-product small-lot production of semiconductor devices increases the number of times the exposure parameters must be extracted, a task which is performed for each reticle, exposure step and exposure device, so that the TAT (turn-around time) for newly ordered/in-process semiconductor devices in increases as well. It is possible to limit the number of times the task of extracting the exposure parameters is performed by fixing the exposure parameters of the exposure devices used for each type of semiconductor device, but variations in the operation ratio of exposure devices occur, which lead to a lower throughput of all exposure steps.
As a way to solve this problem, Aida et al. (Electronic Information Society, Introduction into Response Surface Functions For Statistical Design of Optical Lithography Processes, 1996), for example, have proposed a method for producing response surface functions of CD values, using exposure energy, focus offset and the illumination parameters of the optical projection system (numerical aperture NA and illumination coherency "sgr") as variables, and calculating exposure energy and focus offset from these response surface functions.
To increase the operation ratio of the fabrication equipment, a system for automatically selecting and assigning equipment in accordance with the operation ratio of the fabrication equipment, also referred to as xe2x80x9cdispatchingxe2x80x9d, which depends on certain rules such as xe2x80x9cFIFOxe2x80x9d or xe2x80x9cpriority on delivery timexe2x80x9d, has been implemented (for example, xe2x80x9cSiviewxe2x80x9d, IBM Japan), and is currently used for the assignment of exposure devices.
Furthermore, JP H11-267952A proposes a production control system, in which the fabrication variations in each step are reduced and the quality and yield are improved.
In the fabrication of multiple-product small-lot production of semiconductor devices such as system LSIs, the number of times the task of extracting the exposure parameters is performed for each reticle, exposure step and exposure device for the fabrication of new products, and the TAT of the products are higher than for mass-produced products such as memory devices. By fixing the exposure parameters of the exposure devices used for each type of semiconductor device, the number of times the task of extracting the exposure parameters has to be performed can be reduced, but this causes irregularities in the operation ratio, and leads to a decrease in the throughput of all exposure steps.
In the approach for calculating the exposure energy and focus offset proposed by Aida et al., as mentioned above, it is possible to calculate the optimum values of exposure energy and focus offset due to differences in the illumination parameters of the optical projection system. However, to calculate the exposure energy and focus offset for a plurality of exposure devices is problematic: there are differences between the exposure devices, such as differences in the aberrations of the projection lenses, so that the response surface functions have to be produced and corrected for each exposure device. Furthermore, information regarding the circuit pattern is not taken into account, so that it is not possible to correct fluctuations of the exposure energy and the focus offset that depend on the circuit pattern.
In dispatch systems that have been put into practice, the devices that are used can be assigned based on the operation conditions and in-process information of the current fabrication equipment, but the number of times that the task of extracting the exposure conditions has to be performed cannot be reduced. Accordingly, it is not possible to assign exposure devices for which the setting of the exposure parameters has not been carried out, and such devices cannot be used to diminish the increase in the TAT of semiconductor devices caused by the increase in the number of times that the task of extracting the exposure conditions has to be performed for multiple-product small-lot production.
In JP H11-267952A, a combination of fabrication devices is selected using workmanship data when machining is performed. Because there is no workmanship data in the case of newly ordered/in-process semiconductor devices, this approach cannot be used in such cases.
Moreover, if the miniaturization of the device pattern progresses, even with the same illumination conditions, the process windows will fluctuate depending on differences among the exposure devices due to the aberrations of their projection lenses, so that the production yields for the semiconductor devices will also vary due to the differences among the exposure devices. When forming very detailed circuit patterns, it is necessary to perform exposure processing after comparing the process windows of a plurality of exposure devices, and selecting an exposure device with a large process window, to improve the yield.
The present invention provides a method for lithographic processing of semiconductor devices and an exposure system for use in that process that has a means for calculating the margins of exposure energy and focus, as well as for calculating the optimum values of exposure energy and focus offset, which change depending on the aberration of the projection lenses of the exposure devices; and a means for assigning an exposure device used for such processing, based on the calculated margins of exposure energy and focus.